Error correction codes (ECCs) are widely utilized to reflect data values stored in NVM devices to avoid read errors. Parity is one of the common ECC protection schemes.
For NVM devices that can only be programmed uni-directionally, such as flash memories, a series of data values may be written into data cells of a codeword within a programming cycle. Parity cells in the codewords may be used to store parity information that reflects the data value stored in the data cells. However, the parity cells can only be programmed to correspond with the data value once within a programming cycle. This is because a subsequent write operation to reflect a change of data value normally requires the parity cell of the codeword to be reversely programmed which cannot be achieved by the uni-directionally programmed parity cell of the NVM devices within the programming cycle. So, currently when data cells in a codeword are programmed for a second time, the corresponding parity cell has to be disabled to avoid errors caused by unmatched parity value.
For NVM devices that can be programmed bi-directionally, such as phase change memories (PCM), the parity cells in a codeword have to be programmed every time when a data value is written into the codeword, which may cause reliability problems of the parity cells.